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[VHDL-FPGA-Verilog] MULT

Description: the document used to describe the verilog codes design floating point multiplier in coms design
Platform: | Size: 2351104 | Author: rajapraba | Hits:

[VHDL-FPGA-Verilog] ADS7822-data-collection

Description: ads7822数据采集，verilog语言实现， 采集结果转换为IEEE754 单精度浮点输出！-the ads7822 data acquisition, the Verilog language, collected results into the IEEE754 single precision floating-point output
Platform: | Size: 107520 | Author: seven | Hits:

[VHDL-FPGA-Verilog] float

Description: 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
Platform: | Size: 1024 | Author: 朱文 | Hits:

[VHDL-FPGA-Verilog] float

Description: 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
Platform: | Size: 1024 | Author: 真 | Hits:

[Software Engineering] xjwbwd

Description: 这个fpadd程序应用verilog语言，实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
Platform: | Size: 1024 | Author: TD | Hits:

[VHDL-FPGA-Verilog] Mul32

Description: Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
Platform: | Size: 8192 | Author: lenovo | Hits:

[File Format] fpaddmisc-(1)

Description: VERILOG CODE FOR FLOating point adder
Platform: | Size: 2048 | Author: hari | Hits:

[VHDL-FPGA-Verilog] altfp_mult_DesignExample_ex

Description: 浮点数乘法 verilog语言编写 可直接调用-Floating-point multiplication verilog language
Platform: | Size: 2405376 | Author: linyi | Hits:

[VHDL-FPGA-Verilog] altfp_log

Description: 浮点数 log运算模块 verilog语言编写 可直接调用-Log floating point arithmetic module can directly call verilog language
Platform: | Size: 1223680 | Author: linyi | Hits:

[VHDL-FPGA-Verilog] altfp_mult_abs

Description: 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
Platform: | Size: 324608 | Author: linyi | Hits:

[VHDL-FPGA-Verilog] altfp_matrix_mult

Description: 浮点数 矩阵乘法模块 verilog语言编写 可直接调用-Floating-point matrix multiplication module can directly call verilog language
Platform: | Size: 2248704 | Author: linyi | Hits:

[VHDL-FPGA-Verilog] FFT

Description: VERILOG CODE FOR FLOATING POINT 8 POINT FFT
Platform: | Size: 16083968 | Author: gsp | Hits:

[VHDL-FPGA-Verilog] Float_add

Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder.
Platform: | Size: 12144640 | Author: zhu yue | Hits:

[VHDL-FPGA-Verilog] Verilog_add_div_multi_exp

Description: 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision
Platform: | Size: 5120 | Author: 周和 | Hits:

[Other] float_int

Description: 自己编写的，浮点数与整数之间的转换的Verilog HDL实现-Written by myself, it is converted into Verilog HDL integer floating point implementation
Platform: | Size: 1024 | Author: baijin | Hits:

[VHDL-FPGA-Verilog] fpu_double

Description: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic.
Platform: | Size: 244736 | Author: 丁一 | Hits:

[VHDL-FPGA-Verilog] floatadd

Description: 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
Platform: | Size: 2048 | Author: 小王 | Hits:

[Algorithm] Kalman Filter

Description: 实现单精度浮点的kalman滤波器的verilog方法(Verilog method for realizing single precision floating point Kalman filter)
Platform: | Size: 322560 | Author: sisuozheweilai | Hits:

[Other] fpmul

Description: Verilog语言编写的单精度浮点数乘法器(The Verilog language of single precision floating point multiplie)
Platform: | Size: 1024 | Author: daodaih | Hits:
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